www.siliconstandard.com 1 of 4 SSM9410M re v . 2.02 4/06/2004 n-channel enhancement-mode power mosfet simple d rive r equirement bv dss 30v low o n-resistance r ds(on) 6m w fast s witching i d 18a description absolute maximum ratings symbol units v ds v v gs v i d @ t a =2 5 c i d @ t a =7 0 c i dm a p d @ t a =2 5 c w/ c t stg t j symbol value unit rthj-a thermal resistance junction-ambient 3 max. 50 c /w thermal data parameter total power dissipation 2.5 w -55 to 150 c operating junction temperature range -55 to 150 c linear derating factor 0.02 storage temperature range continuous drain current 3 15 a pulsed drain current 1 80 parameter drain-source voltage gate-source voltage continuous drain current 3 rating 30 18 a 12 advanced p ower mosfets from s ilicon stan dard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the so-8 package is widely preferred for commercial and industrial surface - mount applications and is well suited for low voltage applications such as dc/dc converters. s s s g d d d d so-8 g d s
www.siliconstandard.com 2 of 4 ssm9 41 0m re v . 2.02 4 /06 /2004 electrical characteristics @ t j =2 5 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua 30 - - v d b v dss / d t j breakdown voltage temperature coefficient reference to 25 c , i d =-1ma - 0.01 - v / c r ds(on) static drain-source on-resistance 2 v gs =10v, i d =18a - - 5 m w v gs =4.5v, i d =12a - - 6 m w v gs =2.5v, i d =6a - - 8 m w v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =12a - 47 - s i dss drain-source leakage current (t j =25 o c) v ds =30v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =24v, v gs =0v - - 25 ua i gss gate-source leakage v gs =-- na q g total gate charge 2 i d =18a - 59 95 nc q gs gate-source charge v ds =24v - 10 - nc q gd gate-drain ("miller") charge v gs =4.5v - 23 - nc t d(on) turn-on delay time 2 v ds =15v - 16 - ns t r rise time i d =1a - 12 - ns t d(off) turn-off delay time r g =3.3 w , v g s =10v - 9 6 - ns t f fall time r d =15 w -3 0- ns c iss input capacitance v gs =0v - 5080 8100 pf c oss output capacitance v ds =25v - 660 - pf c rss reverse transfer capacitance f=1.0mhz - 400 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =18a, v gs =0v - - 1.2 v t rr reverse recovery time i s =18a, v gs =0 v , - 43 - ns q rr reverse recovery charge di/dt=100a/s - 39 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 125 c /w when mounted on min. copper pad. 12v 100
www.siliconstandard.com 3 of 4 ssm9 41 0m re v . 2.02 4 /06 /2004 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance v.s. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 30 60 90 120 150 180 210 240 270 0.0 1.0 2.0 3.0 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10v 6.0v 5.0v 4.5v v g =2.5v 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 v ds , drain-to-source voltage (v) i d , drain current (a) t a =150 o c v g =2.5v 10v 6.0v 5.0v 4.5v 3 5 7 9 11 024681012 v gs , gate-to-source voltage (v) r ds(on) (m ) i d =18a t a =25 0 2 4 6 8 10 12 14 16 18 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =18a v g =10v 0 0.5 1 1.5 2 -50 0 50 100 150 t j , junction temperature ( o c) v gs(th) (v)
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 4 of 4 ssm9 41 0m re v . 2.02 4 /06 /2004 fig 9. maximum safe operating area fig 10. effective transient thermal impedance 0.01 0.1 1 10 100 0.1 1 1 0 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 1 0 100 1000 t , pulse width (s) norm alize d th e r m al r e spon se ( r th ja ) p dm duty factor = t/t peak t j = p dm x r thja + t a rthia=125 /w t t 0.02 0.01 0.05 0.1 0.2 duty factor =0.5 single pulse 100 1000 10000 1 5 9 1317212529 v ds , drain-to-source voltage (v) c (pf) f=1.0mhz ciss coss crss 0 4 8 12 16 0 40 80 120 160 q g , total gate charge (nc) v gs , gate to source voltage (v) v ds =15v v ds =20v v ds =24v i d =18a fig 7. gate charge characteristics fig 8. typical capacitance characteristics t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge fig 11. switching time waveform fig 12. gate charge waveform
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